A while back I published a tutorial on the basics of logic gates. The tutorial talks about what logic gates are, truth tables, and active levels.

Then, the tutorial talks about the basic logic gates many of us are familiar with: NOT, AND, OR, NAND, NOR, XOR, and XNOR.

Because of limited space, the post did not cover Boolean algebra, DeMorgan’s theorems, combinational logic, etc. It also leaves out an important and practical part of digital design with gates – the electrical characteristics of logic gates.

This tutorial on logic gates will with leave the topics of Boolean algebra, DeMorgan, etc. for a future tutorial.

This time, we’re going to focus on the important and practical, yet often overlooked, electrical properties and characteristics of logic gates.

**Electrical Properties of Logic Gates**

Logic gates (and other digital logic devices) have their own characteristic voltages and currents.

Toward that end, we’re going to view the inputs and outputs of logic gates as electronic circuits this time rather than from the perspective of truth tables and Boolean expressions.

Knowing the input and output voltages and currents of these devices is essential because things like fan out, power dissipation, noise, and interfacing depend on them.

Let’s start by talking about the differences between two common logic families you’re likely to run into.

**TTL vs CMOS Logic Gates**

The two main logic families that you’re likely to run into, use, and hear about are TTL and CMOS. Each have their own strengths and weaknesses.

**Transistor to transistor logic**, or **TTL** logic gates, are a family of gates which bases itself upon bipolar transistors. It is a mature, robust technology.

**CMOS**, or **complementary metal oxide semiconductor** logic gates are based upon metal oxide semiconductor field effect transistors. These can be fragile. Static electricity on your body can destroy some CMOS gates, so they may require careful handling.

A detailed discussion on bipolar transistors and field effect transistors (or FETs) is beyond the scope of this tutorial, but you can be sure both will eventually show up with their own tutorials.

Let’s quickly gloss over some pros and cons of each.

CMOS logic gates consume less power (this does depend on some factors which we’ll talk about later), have great noise immunity, and work with a wide variety of power supply voltages. However, as we now know, they can be sensitive to static electricity, which can destroy the field effect transistors within the logic gate.

TTL gates have more current-driving capability than CMOS gates and are not sensitive to static electricity. However, they consume more power and have more rigid power supply requirements.

One important takeaway is that transistors are the building blocks of logic gates. Because of this, it is really transistors that are the foundation of all things digital.

On a final note, if you’re not using some of the inputs on a particular gate, you should tie them to the appropriate logic level. This goes for TTL and CMOS. With AND and NAND gates, tie unused inputs to HIGH (use a 1 kΩ resistor with TTL). For OR and NOR gates, tie them to ground.

**Propagation Delay in Logic Gates**

**Propagation delay** is the time required for the output of a gate (or really any digital circuit) to change states after one or more of its inputs changes states.

This occurs because the output of a logic gate cannot respond instantaneously to changes at its input. There is a small delay — usually several nanoseconds — between input changes and output response.

Though the delay is tiny, it can make a difference depending on the number of gates and your application.

Propagation delay is largely due to the charging and discharging of internal capacitances within the transistors that make up the logic gate.

*Figure 1: propagation delay of inverter.*

Figure 1 illustrates the propagation delay of a simple inverter using a timing diagram.

An ideal inverter would change its output at the very instant its input changes. However, as we can see in figure 1, there is a short delay between the changing of the input from low to high and the changing of the output. This difference is the propagation delay of the inverter.

A digital circuit consisting of two or more logic gates (or other digital devices) has a propagation delay that is the sum of all the delays in the input-to-output path.

Consider the circuit in figure 2.

*Figure 2: propagation delay in multiple logic gates.*

Here we have an AND gate and an OR gate. Changes at the AND gate’s inputs (A and B) must propagate through both gates to affect the output. However, a change in input C only needs to pass through the OR gate. Let’s work through the timing diagram one step at a time.

In the diagram above, *t* is time, the *p* subscript stands for propagation, The *HL* subscript means HIGH to LOW, and the *LH* subscript means LOW to HIGH. So, *t*_{pHL }denotes the propagation delay time of the gate switching from HIGH to LOW.

When A goes LOW, the output AB (A AND B) also goes LOW after a short delay. Input C is already LOW. So, the output Y goes LOW after another short delay in the OR gate. The sum of these two delays is the total propagation delay of the circuit.

The HIGH to LOW transition at input B has no effect; there is no difference between 0 AND-ed with 1 and 0 AND-ed with 0. Either way, the result is 0 or LOW.

Then, the LOW to HIGH transition at input C makes the output go HIGH after one propagation delay – the delay of the OR gate. At this point what happens at the AND gate doesn’t matter.

**Logic Gate Fanout**

So far, we’ve assumed that logic gates are able to drive any number of other logic gates attached to their output.

The thing is, gates are electrical devices with finite current-driving capabilities. Because of this, there is a limit to the amount of gates a given logic gate can drive.

The number of gates or loads a logic gate can drive is it’s **fanout**.

Technically, fanout is simply an application of Kirchhoff’s current law (KCL). KCL says that the algebraic sum of currents entering a node must be zero. So, the maximum current a logic gate’s output can safely supply and the current requirements of the load gate it connects to limits the fanout.

For more on KCL, see this circuit analysis tutorial.

Let’s say we have an AND gate driving four other gates (load gates). The AND gate must supply current to the inputs of the other four gates.

Each load gates requires a certain amount of input current which depends on what state the gate is in. The sum of these input currents is the current the driving AND gate must supply. The fanout is determined by the amount of current the driving gate can source without degrading its output voltage.

Figure 3 illustrates this concept with one NAND gate driving other NAND gates. I_{OH} is the output current of the first gate when its output is HIGH. The input current for the other gates is I_{IH }where the subscript IH means input HIGH.

*Figure 3: logic gate fanout.*

Figure 3 shows a NAND gate driving an arbitrary number of other NAND gates. Here, we assume its output is HIGH. This is important because the fanout values of HIGH and LOW states may be different depending on the gate. If this is the case, the smallest value for fanout is used.

So, what happens if we load a logic gate output beyond its fanout capabilities?

This could destroy the output of the driving gate with excessive heat from the current. More likely the performance of the driving gate will degrade because its output voltage degrades. This can affect other parameters, such as noise margin, which we’ll discuss shortly.

**Logic Gate Power Dissipation**

Logic gates require a certain amount of power to operate.

With TTL devices, the supply current differs when its outputs are HIGH vs when they are LOW. Thus, the supply current and power depend on the state of the gate’s output. The power dissipation of TTL gates also depends on the duty cycle of the output. Duty cycle is just the fraction of time the output is HIGH.

CMOS logic gates require very little power when in a static state. That is, when they are not switching from LOW to HIGH and vice versa.

But when the outputs switch more current is drawn. Because of this, CMOS power dissipation depends on the switching frequency of the outputs. This is why the CPU in your computer gets hot and needs cooling. Millions of gates are switching on and off at a very high frequency.

In a CMOS gate, a change of state requires the charging and discharging of internal capacitances, which results in a greater demand on supply current. The faster the gate switches, the more power it needs.

**Noise Margin of Logic Gates**

Electric circuits are susceptible to noise, which is often other stray electrical signals.

These come from the electromagnetic fields of motors, lighting, high-frequency electronic circuits, and even outer space.

Of course, as any experienced circuit designer will tell you, it is impossible to eliminate all noise from a circuit.

Logic gates are no exception.

Because of this, it is desirable to build a certain amount of tolerance into logic gates and other digital devices.

This is the **noise margin** of the gate.

In the world of digital, there are only two possible states: on or off, HIGH or LOW, 1 or 0. They all mean the same thing.

But what defines a HIGH and a LOW?

Different devices have difference specs depending on operating voltage, but let’s assume 5 V operating voltage for the purpose of demonstration.

For a certain logic family a HIGH may be anything from 5 V down to 2.7 V and a LOW may be anything from 0 V up to 0.5 V.

But what about everything in between 0.5 V and 2.7 V?

Voltages in this range are invalid. If a logic gate sees an invalid voltage, its operation becomes unpredictable. Now imagine 10,000 gates inside the CPU on your phone all with invalid voltages. Who knows what will happen? Most likely the system will completely crash.

*Figure 4: logic gate noise margin.*

Figure 4 shows this concept.

The gate in part *a* of the figure has noise pushing its operating voltages into the forbidden (or invalid) region because there is no noise margin in the gate.

The gate in part *b* still operates normally even though there is noise because it has a certain amount of noise margin built in.

**It’s Perfectly Logical…**

It’s true that a lot of hobbyists these days seldom use discrete logic gates in their designs. After all, we have powerful microcontrollers and things like Arduino.

However, there are some things one can do with discrete gates that may be cheaper and easier than throwing an Arduino or a PIC at it.

And let’s not forget that your microcontroller, including the one on your Arduino, is made of logic gates. Because of this, using discrete logic in some of your projects can be a good lesson on the basics of how microcontrollers and microprocessors work.

Just be sure to keep their electrical properties in mind when using logic gates.

Next time we talk about logic gates, we’ll get back into the theory which can show you how it may be possible to replace your Arduino with a few gates for simpler applications.

Until then, I’ll ask the same question I asked after the first logic gate tutorial…

Can you replace anything you’re doing on an Arduino or microcontroller with a few simple gates? I’d love to know about it. Drop a comment and share it or share your thoughts on this tutorial.

Sridhar says

lOved reading it! Great job presenting some very interesting stuff in a very Readable and enjoyable format! ? looking forward to reading about how arduIno functions can be replaced by logic gates!

Brian says

Thanks a bunch! Keep checking back for more updates and tutorials on logic gates, Arduino, and other electronics related content. People like you make it worth while.