What a time to be an electronics enthusiast! These days there is no shortage of communication standards and protocols for microcontrollers and other electronic devices. In addition to the I2C specification — the topic of this article, we have SPI, UART, RS-232, CAN, LIN, 1-wire, the ubiquitous USB interface and more.
And these are just wired serial communications. If we throw in wireless and parallel specifications and protocols, the list grows much bigger.
Each of the above have their own pros, cons, and are suitable for different purposes. This article will be an introduction to the I2C specification. You will see I2C written as I2C in many instances and both are technically correct. However, to keep things easy and consistent, we’ll refer to the protocol as I2C in the rest of this article.
Be sure to go until the end for a nice summary on I2C communications and an I2C specifications chart!
The I2C Specification
I2C stands for inter-integrated circuit bus (which is why many refer to it as I2C). Most people pronounce it I squared C.
The standard dates back to the 1980’s when Dutch giant Philips developed it.
At the time, integrated circuits were growing more complex. Along with the additional complexity came higher pin counts. The actual circuitry inside an IC is much smaller than the package it comes in. The problem was that the higher pin counts were forcing IC manufacturers to use larger packaging in order to accommodate all the pins. The I2C standard was an answer to this problem. In an effort to reduce pin counts, Philips developed the standard. We’ll see why I2C can decrease pin counts in a minute.
Multiwire cables don’t work very well beyond a few feet and are awful for use in high speed parallel buses which only work in lengths up to a few inches and require expensive connectors. This issue, along with the IC pin count issue, gave birth to a bunch of simple serial data buses and standards with I2C being one of them.
Rather than running 16 and 32 bit buses (along with additional control lines) between boards and ICs, these serial data buses allow one to use far fewer lines which drastically simplifies manufacturing and the transfer of the data itself.
Philips nixed their semiconductor division (which is now NXP) but I2C is alive and well today.
How the I2C Standard Works
I2C requires only two lines (plus ground) to work. Compare that with 32+ lines for a parallel connection with a modern 32-bit microprocessor.
It is a two-wire serial bidirectional bus that connects ICs, boards (i.e. you can use I2C to connect Arduinos), and other electronic devices. Its also a synchronous bus meaning that the bit transfer is controlled by a clock which the master shares with all devices on the bus. Synchronous devices need a physical line to be dedicated to the clock (like SCL) which provides synchronization between all devices on the bus. But I2C is also asynchronous in the sense that the master can start and stop data transfer at any time.
The two primary lines are the serial data line (SDA) and the clock like (SCL). Both share a common ground. The lines are usually copper paths on a PCB or short segments of twisted pair cable. The I2C standard uses a master-slave configuration which we’ll talk more about in a minute.
Figure 1: Basic I2C block diagram.
Figure 1 depicts the basic gist of how an I2C bus works. Notice the double arrow on the data line (SDA). This indicates that SDA is a bidirectional line.
The SDA and SDL lines are open-drain that use a pull-up resistor to 5 V or whatever the supply voltage is. We’ll say more about open drains shortly.
The I2C bus can accommodate a lot more than just two devices and all circuits that connect to the bus share the two bus lines.
A device on the I2C bus is usually either a master or a slave. The master provides overall control of I2C transmissions and also supplies the clock to any slave devices. Only a master can initiate a data transfer, slaves just respond to read or write commands from the master.
So, what exactly is the “master?”
The master can be an IC made for that purpose; however, it is usually built into a microcontroller or board. In fact, many single chip microcontrollers include an I2C bus as a standard I/O port.
As we can see from figure 1, any device may transmit or receive data in either direction but what’s not obvious from the figure is that only one device can speak at a time.
Let’s go a little deeper into the I2C rabbit hole and get to know the bus on a more intimate level.
Going Further Down the I2C Rabbit Hole
Within the original I2C specification, two main modes of operation exist: standard mode with a maximum clock rate of 100kHz and fast mode with a max clock rate of 400 kHz.
Each device that connects to the I2C bus has a unique address.
More than one master (and also more than one slave) can exist on the same bus. However, one master always has control over the bus. This master is responsible for generating the clock and controlling bus access by initiating and terminating message transfers.
Both SDA and SCL are open-drained and need to be pulled up to Vcc (the source voltage) with a resistor whose value typically ranges from 1 kΩ to 10 kΩ. Generally, the lower the value of the resistor the faster the speed of the bus. Figure 2 illustrates this.
Figure 2: I2C bus with a pull-up resistor. Normally, only SDA needs the pull-up resistor.
In figure 2, devices 1-3 are slaves and the MCU is the master. We can also see a resistor (Rp) “pulling up” SDA to 5 V, which is Vcc in this case. SDA needs only one resistor, regardless of how many devices connect to the bus.
SCL only needs a pull-up resistor if there will be more than one master on the line or when a slave will do clock stretching (more on this later).
In the first case, the resistor is necessary for arbitration purposes if more than one master tries to initiate a data transfer at the same time. The I2C standard contains an arbitration procedure to deal with such events.
In the second case, a receiver (or slave) may not be ready to receive data from the transmitter, so it holds SCL low to “stretch” the clock to delay the transmitter. Figure 3 illustrates the I2C bus with two pull-up resistors.
Figure 3: in this case both lines have pull-up resistors. The second one on SCL is only necessary in the two special circumstances described above.
So, what’s all this open drain stuff?
The drain is one of the terminals on a MOSFET. For a review on MOSFETS check out An Introduction to Transistors. A typical IC is made up of many tiny MOSFETS. The term open drain is engineering speak for a sink on an output pin. By sink, I mean current flows into the pin, not out of it. A current source is the opposite of a current sink. In a current source, current flows out of the pin.
Therefore, the term open drain means that part of the output transistor connects directly to a pin that’s on the outside of the IC.
And what about that pull-up resistor?
The pull-up resistor connects to HIGH (which is the same as the supply voltage or Vcc) at one end and connects to one or more external pins of the open-drain devices (via the bus). Thus, if any one of the open-drain devices is set to sink current, current flow for all of the devices sinks to ground.
The I2C bus is idle when both SDA and SCL are HIGH. The master initiates a data transfer by issuing a start condition. A start condition is simply a HIGH to LOW transition on the SDA line while SCL is HIGH. After the start condition, the master sends out an address to reach the right slave on the bus. Once any slave determines the requested address is not its own it disregards all further bus activity until the stop condition (more on this in a sec).
The address is 7 bits with bit 8 being a data direction. Since 27 = 128, an I2C bus can hold up to 128 slave devices, though in practice there are usually a lot less. Also, the I2C specification includes a 10-bit addressing option but it rarely sees use in real life. The data direction dictates whether the master will be writing to the slave or the slave will be reading from the master. A HIGH indicates a write to the slave, and a LOW indicates a slave is reading from the master.
After the address of the slave is sent, the protocol calls for sending a code to identify the register in the slave the master will write to or read from, if the slave has multiple registers. This is part of the data block in figure 4.
The master (which controls the clock or SCL line) sends out the bits one bit per clock cycle with the most significant bit or MSB (for a review on MSB and binary numbers see A Bit of Fun with Binary Number Basics) going first. The values on the SDA line can only change when the SCL line is LOW.
Figure 4 depicts the basics of how this works.
Figure 4: basic I2C protocol diagram. For every 8 bits of data, the receiver or slave sends an acknowledgement (ACK) during the ninth clock cycle by pulling SDA low unless the master or receiver wants to end the transfer. In that case, the master will not acknowledge (this is the NACK in the picture) by keeping SDA high. Note that I2C does support 10-bit addressing but it is not used very often.
The slave will respond with an acknowledgement bit on the SDA line by pulling SDA LOW during the clock’s ninth cycle. The direction bit (R/W or read/write in figure 4) determines whether the master or slave will be the transmitter in the subsequent data transmissions.
Data is transmitted in 8-bit chunks with the MSB first until all of it has been transferred, with an ACK (or a NACK if the transmission is over) after each byte. There is no limit on the number of bytes in a transmission. If any data chunk is not acknowledged, there will be no more data exchanged and the transmission ends.
To end a data transfer, the master will send a stop condition by pulling the SDA line from LOW to HIGH while the SCL line is at a HIGH. If the master wishes to change the direction of the data transmission it will send another start condition, so it doesn’t have to release control of the bus.
Figure 5 gives more detail on the read format of the I2C protocol. Below that, figure 6 shows some detail about the start and stop conditions.
Figure 5: more detail on I2C transmissions. A start condition occurs if the data line (SDA) goes LOW while the clock (SCL) is HIGH. If it rises while the clock is HIGH a stop condition ensues. Other than these two special states, the data line can only change when the clock line is LOW.
Figure 6: a close up of the I2C protocol start/stop conditions. The master initiates both conditions. In part a, SDA transitions from HIGH to LOW while SCL is HIGH. In part b, SDA transitions from LOW to HIGH while SCL is HIGH.
At first, this process can seem complicated so let’s summarize it.
I2C Data Transmission Steps
- The master initiates a transmission by sending a start condition. This is done by pulling SDA from HIGH to LOW while SCL is HIGH. Every slave on the bus sees the start condition.
- Next, the master sends the address of the slave (can be 7 or 10 bits but usually 7, so we’ll assume 7 from here on) with a read/write bit as the eighth bit.
- The slave with the requested address will acknowledge by pulling the SDA line LOW for one clock cycle.
- If the slave has more than one register, the master sends the register number of the register it wants to write to or read from.
- The master sends or receives the data in 8-bit chunks.
- After each 8-bit chunk of data transmits, the receiver acknowledges it by pulling SDA LOW for one clock cycle.
- When the master finishes, it sends the stop condition by pulling SDA from LOW to HIGH while SCL is HIGH.
- All changes on SDA line (except start and stop conditions) must occur when SCL is LOW.
I2C Clock Rates and Speed
Recall that earlier we established two different speeds. Standard mode sports a maximum clock rate of 100 kHz and fast mode a max clock rate of 400 kHz.
There are also newer, faster versions of the I2C standard.
Fast plus mode tops out at 1 MHz while high speed mode can hit 3.4 MHz. Ultra-fast mode is the newest kid on the block boasting speeds up to 5 MHz.
One important note is that older I2C devices won’t operate at the higher speeds. Becasue of this, communication on the bus must take place at a rate that’s compatible with all the devices. So, the slowest device limits the top speed of the whole bus.
I2C Speed and Bus Capacitance
The speed also depends on bus capacitance. Recall that SDA and SCL are physical lines which are either traces on a PCB or a twisted pair cable. The fact that both scenarios have two conductors close in proximity that are separated by an insulator means there will be parasitic capacitance. Other factors also have an effect on parasitic capacitance.
The maximum capacitive load for the I2C bus is 400 pF for standard and fast mode and 550 pF for fast mode plus. The number of devices on the bus and the length of the cables or board traces affect the capacitance. The lower the bus capacitance the better and the faster the speed will generally be for any given flavor of I2C.
While most hobbyists probably won’t have to worry about going over the bus capacitance limit it is worth mentioning. There are a few work-arounds for this but since this is an introduction to I2C, that’s all we’ll say about bus capacitance.
The chart below shows some of the I2C specs and info you’ll need to know about.
At first, I was going to have the headline say something corny like now you see I2C, but I decided to spare the lame attempt at humor and be boring.
Anyway, like all things in the wonderful world of electronics there is more to say about the I2C standard and protocol.
But, this is just an intro to I2C so we’re going to stop here to avoid information overload.
Until next time, feel free to post your questions about I2C or share your projects that use I2C.
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